High-speed electrical signaling: overview and limitations

dvances in IC fabrication technology , coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer to peripheral connections, 1 local area networks, 2 memory buses, 3 and multi-processor interconnection networks. 4 Designers are concerned that these links will soon reach the fundamental limits of electrical signaling. In this article, we examine the limitations of CMOS implementations of high-speed links and show that the links' performance should continue to scale with technology. To handle the interconnects' finite bandwidth, however, requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies , are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling components are implemented as macro cells, integrated on the same die with a microprocessor or signal processing block. For this reason, we do not address bipolar or GaAs Gbps links. Figure 1 shows the components of a sig-naling system: transmitter, channel, and receiver. The transmitter converts digital information to a signal (waveform) on the transmission medium, or communication channel. This channel is commonly a board trace, coaxial cable, or twisted-pair wire. The receiver on the other end of the channel restores the signal, by sampling and quan-tizing it, to the original digital information. Clock generation and timing recovery are tightly coupled to signal transmission and reception. The timing recovery, often embedded in the receiving side, adjusts the phase of the clock that strobes the receiver. The receiver samples the signal waveform at the optimal position. Before discussing the performance of these components, we first need a metric that indicates how a CMOS circuit's performance scales with technology. CMOS performance metric. Basic circuit speed improves as technology scales. Fortunately, all CMOS circuit delays scale roughly the same way; thus, the ratio of a circuit's delay to a reference circuit remains comparable. We exploit this with a metric called a fan-out of four (FO-4) delay. A FO-4 delay is the delay through one stage in a chain of inverters, in which each inverter drives a capacitive load (fan-out) four times larger than its input capacitance. Figure 2a illustrates the normalized delay of various circuit structures versus technology and voltage …